A tristate bus is a conductor to which are connected the outputs of a plurality of tristate drivers. Each tristate driver can adopt any one of three states which are: two active states, one asserting a logic "1" on the bus, and one asserting a logic "0" on the bus, and a high impedance state in which the driver has no influence on the logic state of the bus and imposes substantially no load on any other driver driving the bus to a logic level. In operation usually either only one of the drivers is active while the others are in the high impedance state, or all of the drivers are in the high impedance state. In the latter case the potential on the bus may drift to a value intermediate between the "0" and "1" logic levels. That may be undesirable for circuits receiving data from the bus because the logic level on the bus is undefined. For example, an intermediate level on the bus may cause both the n-channel and p-channel transistors in a CMOS logic gate to be turned on, which is wasteful of power and may even destroy the transistors. To alleviate those problems a keeper circuit is attached to the bus. A keeper is a circuit that latches the logic level placed on the bus by an active tristate driver and maintains that logic level on the bus after that driver is switched to its high impedance state until that driver or one of the other drivers is switched to the other logic level.
A need for the present invention arises in integrated circuits that have tristate buses and that have built-in scan test facilities of the type in which test data is shifted directly into latches of the integrated circuit. Such latches may be used otherwise in the normal functioning of the circuit or may be specially provided. Test data in the form of particular patterns of bits, known as a test vector, is shifted into the latches and is then presented to the combinational logic and conductors of the circuit. The emerging pattern of bits is captured by the latches and the captured pattern of bits is then shifted out of the circuit to be analysed to check that the circuit is functioning correctly. The test bit patterns and analysis are usually provided by a suitably programmed computer. To test a circuit fully many different or all possible scan vectors have to be presented to the circuit and the results from each analysed.
The scan testing of circuits having a tristate bus has particular problems. In most circuits many, typically 10%, of the scan vectors applied to the logic of the circuit result in all the tristate drivers connected to the bus being switched to their high impedance state. When a test vector causes all the tristate drivers to be switched to the high impedance state, the value on the bus is that maintained on the bus by its keeper which is the value placed on the bus in response to the previous test vector. Test pattern generation and analysis programs do not, however, take into account values stored in the circuit from previous test vectors. Therefore when all the tristate drivers are in the high impedance state, the value on the bus is undefined as far as the program is concerned making it impossible to test combinational logic that takes the value on the bus as an input. The tristate drivers themselves are also difficult to test. A test of a tristate driver is to enable that driver only, apply a known value to its input and check the value the driver outputs to the bus or some value derived by the circuit from that value. If the bus has a keeper, however, it is not clear whether a value detected at the output of an enabled tristate driver is that at its input or whether the detected value is that maintained on the bus by the keeper from an earlier test because the driver is faulty and is in fact in the high impedance state.